1. Field of the Invention
The present invention relates generally to semiconductor memory devices, and more particularly to an electrically erasable and programmable nonvolatile semiconductor system including an array of memory cell transistors.
2. Description of the Related Art
With the increasing need for high performance and high reliability of digital computer systems, it is becoming more necessary to develop a large-capacity non-volatile semiconductor memory that can be an alternative to the existing external data-storage medium, such as a magnetic diskette, a fixed disk unit (which is also called the "hard disk unit"), or the like.
Recently, to fulfill the demand, a specific electrically erasable programmable non-volatile read-only memory (EEPROM) has been developed, wherein the integration density of memory cells is greatly enhanced by reducing the number of transistors required to form the cell array on a chip substrate of limited size. The EEPROM of this type is generally called a "NAND-cell type EEPROM" or "NAND type EEPROM," wherein a plurality of series circuits of floating gate tunneling metal oxide semiconductor (FATMOS) field effect transistors each serving as a 1-bit storage cell are arranged so that each of these circuits is connected to a corresponding bit line via a switching transistor. The switching transistor is rendered conductive, when designated, thereby to selectively connect a series circuit of memory cell transistors to a corresponding bit line associated therewith, and is called a "select transistor." The series cell-transistor circuits with the select transistors are called the "NAND cell units" in most cases.
Each NAND cell unit may include four, eight, or sixteen memory cell transistors, each of which has a control gate connected to a corresponding word line and a floating gate that may be charged with charge carriers selectively. Since each "memory cell" includes only one transistor, the integration density of the EEPROM can be improved to increase the total storage capacity thereof.
With presently available NAND type EEPROMs, the remaining non-selected memory cell transistors in each NAND cell unit serve as the "transfer gates" for transferring a data-bit to a target cell being presently selected during a write operation. Looking at a certain NAND cell unit, a select transistor turns on, causing this cell unit to be coupled to a corresponding bit line associated therewith. When a given cell transistor is selected, those non-selected memory cell transistors located between the select transistor and the selected cell transistor are rendered conductive (turn on). If a 1-bit data to be written (write-data) is of a specific logical level ("1" or "0," typically "1"), a data voltage supplied from the bit line is transferred to the selected cell transistor through the non-selected cell transistors. Charge carriers are injected from the drain to the floating gate of the selected cell transistor, charging the floating gate. The resultant threshold voltage of the selected cell transistor changes, causing the write-data to be programmed into the selected cell transistor.
To improve the operating reliability, the non-selected cell transistors serving as "data-transfer gates" during a write (program) or read operation are compelled to meet the following specific requirement: they are limited in variation of threshold voltages thereof. The threshold voltages of these cell transistors should not vary to fall out of a predetermined range (allowable variation range). Otherwise, the write-data to be programmed in the selected cell transistor itself will be varied in potential among the NAND cell units, with the result of the programming reliability being decreased.
With a presently available programming technique for NAND type EEPROMs, it is not easy to meet the above requirement. This may be because the number of memory cell transistors on a chip substrate tend to differ from one another due to inherent deviation either in the manufacturing process or in the physical conditions or therefore less than optimal. Such threshold-voltage variation undesirably permits the coexistence of an easy-to-write cell and a difficult-to-write cell on the same chip substrate, which makes it difficult for an access operation to maintain consistency and uniformity throughout the cell transistors. The resultant operating reliability can no longer be excellent as required.
A similar problem exists during an erase operation. The resulting threshold voltage of a once-erased cell transistor--i.e., a cell transistor into which a logic "0" has been written--should be potentially greater than a predetermined negative level. Otherwise, a sufficient erase performance cannot be achieved; in the worst case, this may lead to the generation of an erase error. The threshold voltage of the erased cell transistor will affect the actual amount of a current (readout current) that may flow therein during a read period, which amount has a direct relation to the data-accessing speed of EEPROMs. In this respect, the threshold-value control is very important. If an insufficiently erased memory cell remains after the erase operation, its resulting threshold voltage will increase beyond the upper-limit of the allowable variation range when a logic "1" is written thereinto during a subsequent program period. Such surplus of the threshold voltage causes the excess-write generation ratio to rise undesirably. As the integration density of the NAND type EEPROMs increases, the threshold-voltage control architecture for memory cells during write/erase operations becomes critical.